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NXP Semiconductors /QN908XC /SCT0 /INPUT

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Interpret as INPUT

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (AIN0)AIN0 0 (AIN1)AIN1 0 (AIN2)AIN2 0 (AIN3)AIN3 0 (AIN4)AIN4 0 (AIN5)AIN5 0 (AIN6)AIN6 0 (AIN7)AIN7 0 (AIN8)AIN8 0 (AIN9)AIN9 0 (AIN10)AIN10 0 (AIN11)AIN11 0 (AIN12)AIN12 0 (AIN13)AIN13 0 (AIN14)AIN14 0 (AIN15)AIN15 0 (SIN0)SIN0 0 (SIN1)SIN1 0 (SIN2)SIN2 0 (SIN3)SIN3 0 (SIN4)SIN4 0 (SIN5)SIN5 0 (SIN6)SIN6 0 (SIN7)SIN7 0 (SIN8)SIN8 0 (SIN9)SIN9 0 (SIN10)SIN10 0 (SIN11)SIN11 0 (SIN12)SIN12 0 (SIN13)SIN13 0 (SIN14)SIN14 0 (SIN15)SIN15

Description

SCT input register

Fields

AIN0

Input 0 state. Input 0 state on the last SCT clock edge.
AIN1

Input 1 state. Input 1 state on the last SCT clock edge.
AIN2

Input 2 state. Input 2 state on the last SCT clock edge.
AIN3

Input 3 state. Input 3 state on the last SCT clock edge.
AIN4

Input 4 state. Input 4 state on the last SCT clock edge.
AIN5

Input 5 state. Input 5 state on the last SCT clock edge.
AIN6

Input 6 state. Input 6 state on the last SCT clock edge.
AIN7

Input 7 state. Input 7 state on the last SCT clock edge.
AIN8

Input 8 state. Input 8 state on the last SCT clock edge.
AIN9

Input 9 state. Input 9 state on the last SCT clock edge.
AIN10

Input 10 state. Input 10 state on the last SCT clock edge.
AIN11

Input 11 state. Input 11 state on the last SCT clock edge.
AIN12

Input 12 state. Input 12 state on the last SCT clock edge.
AIN13

Input 13 state. Input 13 state on the last SCT clock edge.
AIN14

Input 14 state. Input 14 state on the last SCT clock edge.
AIN15

Input 15 state. Input 15 state on the last SCT clock edge.
SIN0

Input 0 state. Input 0 state following the synchronization specified by INSYNC.
SIN1

Input 1 state. Input 1 state following the synchronization specified by INSYNC.
SIN2

Input 2 state. Input 2 state following the synchronization specified by INSYNC.
SIN3

Input 3 state. Input 3 state following the synchronization specified by INSYNC.
SIN4

Input 4 state. Input 4 state following the synchronization specified by INSYNC.
SIN5

Input 5 state. Input 5 state following the synchronization specified by INSYNC.
SIN6

Input 6 state. Input 6 state following the synchronization specified by INSYNC.
SIN7

Input 7 state. Input 7 state following the synchronization specified by INSYNC.
SIN8

Input 8 state. Input 8 state following the synchronization specified by INSYNC.
SIN9

Input 9 state. Input 9 state following the synchronization specified by INSYNC.
SIN10

Input 10 state. Input 10 state following the synchronization specified by INSYNC.
SIN11

Input 11 state. Input 11 state following the synchronization specified by INSYNC.
SIN12

Input 12 state. Input 12 state following the synchronization specified by INSYNC.
SIN13

Input 13 state. Input 13 state following the synchronization specified by INSYNC.
SIN14

Input 14 state. Input 14 state following the synchronization specified by INSYNC.
SIN15

Input 15 state. Input 15 state following the synchronization specified by INSYNC.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data